PDK Enablement Engineering Specialist

February 19, 2026

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role is for an existing vacancy PDK Enablement Engineering Specialist Job Description Summary As a PDK enablement engineering specialist, you will provide and support the tools and foundry files to enable the circuit implementation teams who build circuits used in cars, cell phones, data centers, etc. using the latest fabrication technologies: finfet, gate all-around, and using the latest Cadence software tools, including AI. Job Description Cadence Design Systems is seeking PDK enablement engineering specialists to enable foundry PDKs and support the growing analog design and custom layout team building IP using the Cadence design tools (Virtuoso, Pegasus, Quantus, etc.) to build high speed interfaces used in chips found in cars, cell phones, data centers, etc. You will get the opportunity to collaborate with circuit implementation experts to contribute to the development of exciting chips, work with the best-in-class EDA tools and interact with the Cadence engineering team using developing those tools to improve those tools. The PDKs installed cover the latest technologies offered from all leading edge foundries in gate all-around and finfet nodes, as well as 2D and 2.5D packaging as well as 3D IC stacking. PDK enablement task The PDK enablement team is a part of the Cadence Design IP development group responsible for downloading, formatting, installing, QA and testing, releasing, and maintaining foundry data. We analyze initial PDKs and following versions to understand the impact of the design PDK, models, DRC, LVS and extraction rules and decks, reliability requirements on design and share this knowledge with the design teams. Examples of foundry data include physical verification decks, device models, extraction tech files, and Virtuoso PDKs. Those are the fundamental building blocks on which all the design teams rely to build their circuits. We also create and use existing automation and regression routines to ease the installation and ensure the operation of collateral with various tool versions. The quality, accuracy and reliability of the PDK is critical to the efficiency and quality of the circuit design. We customize the foundry collateral to improve the design team efficiency and the design quality. The team interacts with the foundries about the PDK and foundry data, discussing novelties, issues, bugs, etc. The team also interacts with Cadence R&D teams on tool development, based on PDK learnings. Additional <ul><li>BSEE, MSEE</li><li>Previous experience in PDK enablement</li><li>Knowledge of analog design and layout tools and flows</li><li>Exposure to Cadence Virtuoso Layout and physical verification tools is a plus</li><li>Team player, driven, self-motivated, innovative and autonomous</li><li>Attention to details</li><li>Excellent communication, presentation and customer service skills </li></ul>== Spécialiste en déploiement et développement de PDK Sommaire En tant que spécialiste en spécialiste des PDK, vous déploierez, développerez et founirez du support des PDKs des fonderies nécessaires aux équipes qui conçoivent les circuits intégrés et leurs layouts utilisés dans les voitures, les téléphones portables, les centres de données, etc., en utilisant les dernières technologies de fabrication : FinFET, Gate All-Around, et les outils logiciels Cadence les plus récents, y compris l'IA. Description Du Poste Cadence Design Systems recherche des ingénieurs spécialisés dans les PDK pour bâtir et supporter les fichiers et outils nécessaires à la conception de circuits intégrés dans les fonderies les plus avancées. Ces fichiers seront utilisés par les équipes de conception et de layout analogique. Cette équipe développe des circuits (IP) à l'aide des logiciels Cadence (Virtuoso, Pegasus, Quantus, etc.) afin de créer des interfaces à haut débit utilisées dans les puces présentes dans les automobiles, les téléphones portables, les centres de données, etc. Vous aurez l'opportunité de collaborer avec des experts en conception et layout de circuits pour contribuer au développement de puces innovantes, de travailler avec des logiciels de pointe et d'interagir avec l'équipe de conception des logiciels de Cadence pour améliorer ces outils. Les PDK concernent les dernières technologies proposées par les fonderies leaders du marché, notamment les nœuds Gate All-Around et FinFET, ainsi que le packaging 2D et 2.5D et l'empilement de circuits intégrés 3D. Tâches de l’équipe de déploiement et de développement des PDK L'équipe responsable des PDK fait partie du groupe de développement de circuits IP de Cadence Design Systems. Elle est responsable du téléchargement, du formatage, de l'installation, de l'assurance qualité, des tests, de la publication et de la maintenance des données de fonderie. Nous analysons les PDK reçus et leurs versions ultérieures afin de comprendre l'impact des PDK de conception, des modèles, des règles de conception (DRC), de la vérification du niveau de laboratoire (LVS), des règles et fichiers d'extraction, ainsi que des exigences de fiabilité sur la conception. Nous partageons ensuite ces connaissances avec les équipes de conception. Les PDKs comprennent notamment les fichiers de vérification physique, les modèles de composants, les fichiers techniques d'extraction et les fichiers de Virtuoso. Ce sont les éléments fondamentaux sur lesquels s'appuient toutes les équipes de conception pour construire leurs circuits. Nous créons et utilisons également des scripts d'automatisation et de régression afin de simplifier l'installation et d'assurer le bon fonctionnement des ressources avec différentes versions d'outils. La qualité, la précision et la fiabilité des PDK sont essentielles à l'efficacité et à la qualité de la conception des circuits. Nous personnalisons les PDKs afin d'améliorer l'efficacité des équipes de conception et la qualité des designs. L'équipe interagit avec les fonderies au sujet du PDK en discutant des nouveautés, des problèmes, des bogues, etc. Elle collabore également avec les équipes de R&D de Cadence sur le développement d'outils, en s'appuyant sur les enseignements tirés du PDK. Profil Recherché <ul><li> Diplôme en génie électrique ou électronique (BSEE ou MSEE)</li><li> Expérience en support CAD analogique (design, layout) ou en PDK</li><li> Excellente compréhension de la conception de circuits et du layout</li><li> La connaissance des outils de conception Cadence Composer Schematic et Virtuoso Layout et des outils de simulation et de vérification physique est un atout</li><li> Esprit d'équipe, dynamisme, autonomie, esprit d'innovation</li><li> Excellentes compétences en communication, présentation et service client </li></ul>The annual salary range for MOUNT-ROYAL 01 (Montreal) and BC is 89,600.00 - 166,400.00 CAD Annual. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and holidays, leave of absence programs, Registered Retirement Savings Plan (RRSP), Tax Free Savings (TFSA) plan for post-tax investment savings, Employee Stock Purchase Plan, group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents. Cadence also offers employee and dependent Life insurance, and short-term and long-term disability. In addition, Cadence provides Global Travel Medical coverage, Business Travel Accident Insurance, and a funded Lifestyle Spending Account (LSA). We’re doing work that matters. Help us solve what others can’t. We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

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